As the operating speed of integrated circuit devices continues to increase, it may become increasingly important to provide duty cycle correction for clock sources. In particular, when a clock signal is received from internal or external of the integrated circuit and has a duty cycle that is different from 50%, it may become important to correct the duty cycle to 50%. Duty cycle correction systems and methods for clock signals are described in U.S. Pat. Nos. 4,527,075 to Zbinden, entitled Clock Source with Automatic Duty Cycle correction; 5,491,440 to Uehara et al., entitled Automatic Clock Duty Cycle Adjusting Circuit; 5,572,158 to Lee et al., entitled Amplifier with Active Duty Cycle correction; and 5,757,218 to Blum, entitled Clock Signal Duty Cycle correction Circuit and Method. Duty cycle correction systems and methods may be applied to integrated circuits including logic, microprocessor and memory integrated circuits and integrated circuits that combine two or more of these or other functions.
One type of memory integrated circuit to which duty cycle correction systems and methods may be applied employs the Rambus technology marketed by Rambus, Inc. of Mountain View, Calif. The Rambus technology is described in U.S. Pat. Nos. 5,473,575 to Farmwald et al.; 5,578,940 to Dillion et al.; 5,606,717 to Farmwald et al. and 5,663,661 to Dillion et al. A device embodying the Rambus technology is an example of a packet type integrated circuit memory device, because each integrated circuit receives data and addresses in packet units in a normal mode of operation. The packet is received by the Rambus device which generates internal control signals, internal data signals and internal address signals to carry out the corresponding operation of the packet. For example, the packet may include data, address and control signals for a write operation.
FIG. 1 is a block diagram of an input receiver for an integrated circuit such as a Rambus memory device. As shown in FIG. 1, an input receiver 101 receives a clock signal PCLK, data DB and a reference voltage Vref. The input receiver 101 converts the voltage level of the data DB and outputs the result as complementary data signals DO and DO. For a Rambus device, the data DB may have Transistor-Tranisistor logic (TTL) levels and the data output DO, DO may have Complementary Metal Oxide Semiconductor (CMOS) logic levels. Thus, the input receiver 101 amplifies the difference between the input data DB and the reference voltage Vref to convert the input data DB from To TTL levels to CMOS levels, and outputs the data DO and DO at CMOS levels. The clock signal PCLK preferably is a duty cycle-corrected clock signal.
Notwithstanding the provision of a duty cycle-corrected clock signal, it still may be difficult to operate integrated circuits at high speeds such as several hundred megaHertz. It may be particularly difficult to operate integrated circuits at high speeds when data is processed at both the rising and the falling edges of a clock signal. In particular, as shown in FIG. 2A, when duty cycles of the data DB and the clock signal CLK are both 50%, the sum of the setup time ts and the hold time th of the data DB may equal 50%. Thus, a maximum margin may be allowed for setup time and hold time. However, as shown in FIG. 2B, if the duty cycles of the data DB and the clock signal CLK are within a range of 40%, the duty cycle of the clock signal CLK may be restored to 50% but the data DB is input to the input receiver 101 as is. Thus, the setup ts and the hold time th may decrease compared to FIG. 2A. Conversely, when the duty cycles of the data DB and the clock signal CLK are within an allowable range of 60%, the setup time ts and the hold time th may increase compared to data having a duty cycle of 50%. The above described increases and decreases may reduce the operating margins of the integrated circuit which may thereby impact the speed and/or performance thereof.